FIG. 1 is a circuit diagram showing a prior art semiconductor memory cell for a static RAM, and FIG. 11 is a circuit diagram showing a memory cell for a static RAM. In the prior art memory device, as shown in FIG. 1, a plurality of memory cells are arranged in the order of a first uppermost memory cell MC1, a second memory cell MC2, . . . and a lowermost memory cell MCn. Further, word lines WL1 to WLn are connected to the memory cells MC1 to MCn, respectively to select the respective memory cell MC. Further, two bit lines BL1 and BL2 are connected to the memory cells MC1 and MC2 in common, and other two bit lines BL1R and BL2R connected to the bit lines BL1 and BL2 are connected to the memory cell MCn. In the above-mentioned connection, a bit line wire parasitic resistance R1 is inevitably present between the two bit lines BL1 and BL1R, and a bit line wire parasitic resistance R2 is inevitably present between the two bit lines BL2 and BL2R. Further, a bit line equalize transistor T5 is connected between the two bit lines BL1 and BL2. A pulse .phi. EQ is inputted to the gate of this transistor T5. A bit line pull-up transistor T3 having a gate to which a pulse .phi.EQ is inputted is connected to the bit line BL1. Another bit line pull-up transistor T4 having a gate to which a pulse .phi.EQ is also inputted is connected to the bit line BL2. In addition, bit line load transistors T1 and T2 are connected to the bit lines BL1 and BL2, respectively. On the other hand, the bit line BL1R is connected to an input/output line IO1 via a column switch transistor T6, and the bit line BL2R is connected to another input/output line IO2 via a column switch transistor T7. Two gates of the column transistors T6 and T7 are connected to a column select signal line CL1. Therefore, bit line wire parasitic capacitances C11 and C21 are inevitably present between the bit lines BL1 and BL2 and ground, respectively and bit line wire parasitic capacitances C12 and C22 are inevitably present between the bit lines BL1R and BL2R and ground, respectively.
In the circuit configuration as described above, the pulse .phi.EQ inputted to the gates of the bit line pull-up transistors T3 and T4 and the bit line equalize transistor T5 is a one-shot pulse given at an address transition or at a data write end in order to turn on momentarily the bit line pull-up transistors T3 and T4 and the bit line equalize transistor T5, respectively. When turned on, the bit line pull-up transistors T3 and T4 initialize voltage or potential of the bit lines BL1, BL2, BL1R and BL2R by pulling up the voltage of the bit lines BL1, BL2, BL1R and BL2R at the address transition or at the data write end. Further, the bit line load transistors T1 and T2 serve to prevent a low-level voltage of the bit lines BL1, BL2, BL1R and BL2R from being dropped excessively at the data read operation and additionally to initialize the bit line voltage at the address transition or at the write end, in the same way as with the case of the pull-up transistors T3 and T4. On the other hand, the bit line equalize transistor T5 initializes the bit line voltage in such a way that the bit lines BL1 and BL2 are connected to each other momentarily at the address transition or at the write end to transfer an electric charge from the high level side to and the low level side between the bit lines BL1, BL2 and BL1R, BL2R, respectively (i.e., the voltage amplitude between a pair of the bit lines are reduced momentarily), so that the bit line voltages can be inverted at high speed at the data read operation.
Here, the assumption is made as follows: when the memory cell MC1 is selected in the write status, a high level voltage is applied to the bit lines BL1 and BL1R and a low level voltage is applied to the bit line BL2 and BL2R so that a data "0" is written to the memory cell MC1. In this status, when the write status changes to the read status and an address changes so that the memory cell MC1 becomes a non-selected status and the memory cell MCn is selected, an information recorded in the memory cell MCn is outputted with the bit lines BL1 and BL1R set at the low level and with the bit lines BL2 and BL2R set at the high level. Here, the transistors T1 to T5 are all NMOS transistors. FIG. 3 is a waveform diagram showing change in voltage level on the bit lines BL1, BL2, BL1R and BL2R, respectively in the above-mentioned conditions.
When the write status changes to the read status under the condition that a supply voltage Vcc is applied to the word line WL1 and thereby the memory cell MC1 is selected, the one-shot pulse .phi.EQ the same in level as the supply voltage Vcc is generated to turn on the bit line pull-up transistors T3 and T4 and the bit line equalize transistor T5. At this time, the bit line BL1 at the high level and the bit line BL2 at the low level are equalized through the bit line equalize transistor T5, so that an electric charge transfers from the high level side to the low level side to drop the high level on the bit line BL1 to the low level and to raise the low level on the bit line BL2 to the high level. At the same time as the equalization, the bit lines BL1 and BL2 are pulled up to a voltage (supply voltage Vcc--threshold voltage V.sub.THN) by the bit line load transistors T1 and T2 and the bit line pull-up transistors T3 and T4. On the other hand, the bit lines BL1R and BL2R follow the bit lines BL1 and BL2 (the voltage level changes in the same way). The follow-up characteristics are determined by a time constant of the bit line wire resistance and the bit line wire capacitance. Therefore, the follow-up speed increases with decreasing product of both. In other words, the bit line time constant decreases and thereby the follow-up characteristics is improved with decreasing bit line wire parasitic resistances R1 and R2 and the bit line wire parasitic capacitances C1 and C2. Further, when the word line WL1 changes to the low level and the word line WLn is activated, the memory cell MCn is selected instead of memory cell MC1. As a result, a data stored in the memory cell MCn is transmitted to the bit lines BL1R and BL2R, so that the data access to the memory cell MCn is made and thereby the levels on the respective bit lines BL1, BL2, BL1R and BL2R are all determined.
Conventionally, the bit line equalize transistor T5, the bit line load transistors T1 and T2 and the bit line pull-up transistors T3 and T4 of three different functions are all arranged as shown in FIG. 1 from the standpoint of an easiness in layout. In practice, all the transistors of three functions are arranged together on the uppermost side (on the side of the memory cell MC1) or the lowermost side (on the side of the memory cell MCn) of the bit lines BL1, BL2, BL1R and BL2R and connected to the bit lines. As a result, a pull-up current Ipu and an equalize current Ieq flow through the bit lines BL1, BL2, BL1R and BL2R by way of routes as shown in FIG. 4, during all the above-mentioned data write and read operation. In more detail, in FIG. 4, the equalize current Ieq flows from the bit line wire parasitic capacitances C12 and C11 to the bit line wire parasitic capacitances C21 and C22 through the bit line BL1R, the bit line wire parasitic resistance R1, the bit line BL1 and the bit line equalize transistor T5, the bit line BL2, the bit line wire parasitic resistance R2 and the bit line BL2R, Therefore, the electric charge on the bit lines BL1 and BL1R is discharged and that on the bit lines BL2 and BL2R is charged. On the other hand, the pull-up current Iup flows from the bit line pull-up transistor T3 and the bit line load transistor T1 to the bit line BL2, the bit line wire parasitic resistance R2 and the bit line BL2R through the bit line BL1, the bit line wire parasitic resistance R1, the bit line BL1R and the bit line equalize transistor T5. Therefore, the bit line wire parasitic capacitances C11, C12, C21 and C22 are charged. On the other hand, the pull-up current Ipu flows from the bit line pull-up transistor T4 and the bit line load transistor T2 to the bit line BL2, the bit line wire parasitic resistance R2 and the bit line BL2. Therefore, the bit line wire parasitic capacitances C21 and C22 are both charged.
Recently, with increasing memory capacity of the memory integrated circuit device, the number n of the memory cells arranged in the bit line direction increases in proportion thereto. FIG. 5 shows a memory cell array configuration of a 4 Mbit SRAM. In each memory cell array, a bit line precharge section BLPC, a bit line equalize section BLEQ, a bit line load section BLL and the memory cell section are arranged in sequence, and further a column switch section CSW, a sense amplifier section SA and a data bus section DB are connected in sequence under the memory cell section MC. A row of the memory cell section MC is selected by a row decoder section RD. The memory cell section MC is composed of cells having 128.times.32 sections in column and 1 k cells in row.
With the advance of the larger memory capacitance, the number of the memory cells arranged in the bit line direction has increased more and more recently, with the result that it has become impossible to disregard the influence of the bit line wire parasitic resistances R1 and R2 and the bit line wire parasitic capacitances C11 to C22 (so far disregarded) upon the operation of the bit lines BL1, BL2, BL1R and BL2R.
FIG. 3 is a waveform diagram for assistance in explaining the above-mentioned influence. When the write status changes to the read status under the condition that the supply voltage Vcc is applied to the word line WL1 and thereby the memory cell MC1 is selected, the one-shot pulse .phi.EQ of supply voltage Vcc is generated and applied to the gates of the bit line pull-up transistors T3 and T4 and the bit line equalize transistor T5, so that these transistors are all turned on. At this time, the bit line BL1 at the high level and the bit line BL2 at the low level are equalized in potential level by the bit line equalize transistor T5. Accordingly, an electric charge transfers from the high level side to the low level side, so the bit line BL1 drops from the high level to the low level, and the bit line BL2 rises from the row level to the high level. Upon equalization, the bit lines BL1 and BL2 are pulled up in level to the voltage (supply voltage Vcc--threshold voltage V.sub.THN) by the bit line load transistors T1 and T2 and the bit line pull-up transistors T3 and T4. On the other hand, the potential of the bit lines BL1R and BL2R follows that of the bit lines BL1 and BL2, respectively. In this case, however, when the selection status of the memory cell MC1 changes to that of the memory cell MCn arranged farthest away from the memory cell MC1 now being selected, since the bit line wire parasitic resistances R1 and R2 and the bit line wire parasitic capacitances C11, C21, C12 and C22 are large, the follow-up characteristics from the bit lines BL1R and BL2R to the bit lines BL1 and BL2 are slow in operation. This is because the bit line load transistors T1 and T2, the bit line pull-up transistors T3 and T4 and the bit line equalize transistor T5 are all arranged on the uppermost side of the bit lines BL1, BL2, BL1R and BL2R, so that the bit line wire parasitic resistances R1 and R2 and the bit line wire parasitic capacitances C11 to C22 corresponding to 1000 cells arranged between the uppermost position and the memory cell MCn are inevitably produced to the bit lines. On the other hand, in the write status, the amplitudes of the bit lines BL1, BL2, BL1R and BL2R are all large. Accordingly, it is impossible to sufficiently pull up or equalize the potential of the bit lines BL1R and BL2R, thus causing a problem in that the delay time at the bit line inversion becomes serious whenever the write status changes to the read status.
In addition, since the bit line load transistors T1 and T2 are connected to the uppermost position of the bit lines as shown in FIG. 1, when the bit line wire parasitic resistances R1 and R2 increase, there exists another problem in that the low level on the bit lines BL1, BL2, BL1R and BL2R rises in the data write operation. The data write operation can be achieved by turning on the column switch transistors T6 and T7 selected by the column decoder through a writing driver so that either one of a pair of the bit lines changes to the low level. Accordingly, at points far away from the writing driver on the bit lines, the low level of the bit lines at the data write operation rises by the current flowing through the bit line wire parasitic resistances R1 and R2 from the bit line load transistors T1 and T2. This voltage rise in the low level develops high, in particular at the junction point between the memory cell MC1 arranged near the bit line load transistors T1 and T2 and the bit lines BL1 and BL2.
As described above, in the prior art semiconductor memory device, there exists a problem in that the read/write reliability is deteriorated when the memory capacity increases, and further made high speed operation is difficult.